module rom_led_top(
  input clk,
  input rst_n,
  output [3:0] led
);
reg [2:0] ad_i;
reg [22:0] pre_cnt;

wire sys_clk;
//wire [3:0]led = [3:0]dout_o;

    GW_PLL ul(
        .clkout(sys_clk), //output clkout
        .clkin(clk) //input clkin
    );


    GW_ROM data_rom(
        .dout(led), //output [3:0] dout
        .clk(sys_clk), //input clk
        .oce(1), //input oce
        .ce(1), //input ce
        .reset(0), //input reset
        .wre(0), //input wre
        .ad(ad_i) //input [2:0] ad
    );

always@(posedge sys_clk or negedge rst_n) begin
  if (~rst_n) begin
    pre_cnt<=0;
    ad_i<=0;
  end
  else begin
    pre_cnt<=pre_cnt+1;
    if (pre_cnt==0) begin
      ad_i<=ad_i+1;
    end
  end

end

endmodule


